The Heart of 3G Applications
By Holly Bartlett, Thu May 03 00:00:00 GMT 2001

Inside your third-generation mobile device will be a fast, efficient, power-conserving microprocessor. But getting it in there isn?t easy.


In order for the dream of third-generation computing to become a reality, there must be two things in place: wireless broadband connectivity, and sufficient power at the device level to run useful applications.

Of course, not everyone will opt for a device that slices, dices and makes curly fries – some people just want a device that provides reliable telephony. Today’s mobile device offers this already, so I’ll focus on tomorrow’s needs and various approaches to meeting them.

Pre-requisites for 3G


We’ve been sold on the idea of the mobile Internet for years. When the Internet made its big impact in consumer markets during 1997-1998, one of the first questions people asked is how to cut the cords. We realized that if we could take this vast network of information and make it available to anyone regardless of his or her location, its value would be multiplied many times over.

What people ended-up expecting at the time (and did right up through WAP’s debut) was a handheld device that offered (more or less) the same functionality as a desktop connected to the Internet. Unrealistic as it may seem in hindsight, people expected to see a full webpage displayed on a mobile phone's small screen, and for it to be delivered quickly. Cold reality set in when three or four lines of text delivered at a blazing 300-baud was all we could see.

The networks have made a lot of progress since then, as the GPRS systems rolling out today are introducing faster, more useable connections. UMTS and EDGE networks will further enhance services, delivering on our collective need for speed.

But that’s only half of the equation. In order to run things like full color, frames capable web browsers, imaging applications and media players, we’re going to need to put some horsepower into the mobile device. Chipmakers can see the demand coming (and the profit potential it brings), and have been scurrying to develop chips that deliver excellent performance in smaller, more efficient packages.

But it’s not an easy task. Processors of today like Intel’s Pentium series require large amounts of power, generate lots of heat, and weren’t architected for mobile applications.

Still, for compatibility’s sake, a number of companies have chosen to develop x86 (PC-compatible) mobile processors. One such company is Transmeta, who’s taken a rather creative route toward developing a PC-compatible processor, called the Crusoe.

Changing the market


Last year, the semiconductor industry really started paying much more attention to the class of power efficient x86 microprocessors intended for portable applications. The trend started more than a year ago when Transmeta cleverly repainted a bull’s eye labeled 'low power' around the spot where its Crusoe arrow fell short of its x86 competitors on the performance chart.

Besides achieving x86 compatibility through a unique combination of VLIW hardware and dynamic binary compilation firmware (colorfully termed 'code morphing' software), the Crusoe also incorporates advanced power saving features. Not only could it throttle its processor clock according to its level of computing load, it allowed the supply voltage input to the CPU to be reduced as permitted by the lowered clock rate.

Generally, digital chips consume power proportional to clock frequency and the square of the power supply voltage. If running the processor at half its maximum clock rate permits the supply voltage to be lowered by 30% then a total power savings of more than 75% can be realized by doing both instead of the 50% reduction realized from slower clocking alone.

Although Transmeta garnered far more favorable press than actual design wins over the last year, the attention that the mobile x86 processor market received from being suddenly thrust into the spotlight prompted Intel to respond with a comprehensive new mobile processor road map that was unveiled at last October’s Microprocessor Forum.

Of special interest was the disclosure that Intel would develop an entirely new IA-32 (x86) microarchitecture specifically for low power, mobile applications. This is a remarkable turnaround for a market segment that was previously addressed with hand-me-down desktop processor designs and speed grades that were no longer competitive in the mainstream market. Mobility was finally coming into its own.

From the ground up


The split between x86 processor design and mobile markets has two main causes.

The first is that power consumption of x86 desktop processors has grown well beyond the point at which simple requalification of screened parts with lower supply voltages and slap-on power management logic can bring down their power levels enough to be compatible with the battery and thermal dissipation capacity of most portable computers, let alone handhelds. This problem is even more pronounced for hand-held computing applications where x86 compatibility is not usually required. In this way, a multitude of inexpensive, low power RISC processors (such as the ARM-derived design used in the Nokia 9210, for example) are obvious and credible alternatives to x86 CPUs.

The second reason is the growing profit potential of the mobile processor market, as well as the competitiveness of the players. While the desktop processor market is currently experiencing painfully slow growth and intense price competition, the perennially robust mobile market (which is currently dominated by Intel) has much higher prices and margins. It’s no surprise that AMD will target the mobile market first when it rolls out its new 'Palomino' design for laptops later this year.

There is also a potentially large market for low power x86 processors in high-density rack mounted servers that pack many more CPUs in a given amount of floor space than is currently practical with desktop devices.

The degree to which contemporary desktop processors must be derated to bring down power consumption to workable levels for mobile applications is akin to pounding the proverbial square peg into a round hole. It’s not only inefficient, but advances in manufacturing technology will make it even more so in the future.

That mismatch, combined with the growing economic importance of the mobile market to x86 vendors, provides strong incentive to design a new processor core from the ground up to carefully balance power efficiency with performance.

The key: power conservation


For microprocessors, power consumption is dominated by the current consumed to charge and discharge wires and transistors as 0 to 1 and 1 to 0 transitions race around the chip.

The capacitance is minimized by clever logic design, clock gating, and intelligent floor planning to reduce the total length of interconnect. Besides the obvious approach of reducing the global power supply voltage, CPU designers sometimes minimize the switching voltage by the use of what’s called "limited swing signaling." Effective frequency minimization is accomplished by preventing signals from propagating down paths when and where they are not needed.

A second contributor to power consumption is leakage current. Each transistor in a chip leaks a tiny amount of current. Even with the tens of millions of transistors in modern CPUs the power consumption associated with leakage current is generally negligible compared to switching power. However, ultra-low power CPUs are most often put into idle or deep sleep states when not active.

While dynamic power tracks reductions in clock frequency and switching activity, leakage current power remains relatively constant. The larger fraction of the time that a processor spends with its clock slowed or stopped, the more important the magnitude of leakage power becomes to the overall power consumption. Since mobile devices spend most of their time idle, this is an important point.

Leakage power is a function of the overall number and size of the transistors in a chip and increases exponentially with temperature, while generally varying linearly with supply voltage. Unlike switching power, there is generally little that chip designers can do to reduce leakage other than minimize the size and number of logic transistors in the design.

Unfortunately and paradoxically, advances in modern semiconductor technology increase leakage current with each new generation of the manufacturing process.

Design strategy


The forces of semiconductor process evolution and x86 market dynamics are forcing products for the low power mobile markets to diverge from those intended for the higher power desktop and server markets. This is a good thing - it'll ensure products tailored for each market that perform well in their respective capacities.

The increasing importance of leakage current power consumption in current and future processes means that mobile processor designers just cannot throw ever more logic transistors at chasing the tail of diminishing returns of IPC improvement. Success lies instead in maximizing the performance of transistors that are already there. That is best accomplished by attempting to strike a balance between designing for high clock frequency and designing for high IPC.

While it's a difficult job, doing so will usher in a new era of mobility - bringing exciting applications to your mobile device that previously existed only on your desktop PC.

Having worked previously for a large semiconductor manufacturer, Holly Bartlett is now a developer who writes for TheFeature in her spare time.